In order to attain greater integration and higher performance in semiconductor devices, a Surrounding Gate Transistor (“SGT”) that is a vertical gate transistor is disclosed, having a columnar semiconductor formed on the surface of a semiconductor substrate and a gate formed on the side wall thereof so as to surround the columnar semiconductor layer (for example, see Unexamined Japanese Patent Application KOKAI Publication No. H2-188966). In an SGT, the drain, gate and source are arranged in a vertical direction making it possible to greatly reduce the occupied surface area in comparison to traditional planar transistors.
When a large-scale integrated circuit (“LSI”) is created using SGTs, it is indispensable to use SRAM composed in combination with the SGTs as the cache memory thereof. In recent years, there has been extremely strong demand to increase the capacity of SRAM mounted on LSI, so it is essential that SRAM having a small cell surface area be attained even when using SGTs.
FIG. 25A shows an illustrative planar view of a CMOS-type 6T-SRAM containing six transistors designed using SGTs, as exhibited in the embodiment of Unexamined Japanese Patent Application KOKAI Publication No. 117-99311, and FIG. 25B shows a cross-sectional view thereof. The aforementioned SRAM will be described with reference to these drawings. Bit wires 801a and 801b are formed of an N+ diffusion layer, ground potential wiring GND is formed of an N+ diffusion layer 802 and power source potential wiring Vcc is formed of a P+ diffusion layer 803. On top of these diffusion layers, columnar silicon layers are formed constructing access transistors 810a and 810b in order to access memory cells, driver transistors 811a and 811b in order to drive the memory cells, and load transistors 812a and 812b in order to supply electrical charge to the memory cells. Gates 804a, 804b, 804c and 804d are formed to surround these columnar silicon layers. Memory nodes comprise wiring layers 807a and 807b. In the above-described SRAM cell, the various transistors constructing the SRAM have the source, gate and drain formed in a vertical direction on the columnar silicon layers, so it is possible to design small SRAM cells.